M12L64322A |
RFQ for M12L64322A Required Field |
 |
| Product | Manufacturers | Pack | D/C |
| M12L64322A | - | TSOP | 04+ |
The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits. Synchronous design allows precise cycle control wi0th the use of system clock I/O transactions are possible on every clock cycle.Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Features |
| `JEDEC standard 3.3V power supply `LVTTL compatible with multiplexed address `Four banks operation `MRS cycle with address key programs - CAS Latency ( 2 & 3 ) -Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) `All inputs are sampled at the positive going edge of the system clock `DQM for masking `Auto & self refresh `15.6s refresh interval |
|
Parameter |
Symbol |
Value |
Unit |
| Voltage on any pin relative to VSS |
VIN,VOUT |
-1.0 ~ 4.6 |
V |
| Voltage on VDD supply relative to VSS |
VDD,VDDQ |
-1.0 ~ 4.6 |
V |
| Storage temperature |
TSTG |
-55 ~ + 150 |
|
| Power dissipation |
PD |
1 |
W |
| Short circuit current |
IOS |
50 |
MA |
